The present invention relates to a sense amplifier circuit for a reading circuit of a semiconductor memory apparatus, and more particularly to a sense amplifier circuit for a read only memory.
Recent non-volatile memories such as read-only memories (called ROM hereinafter) are required to have large capacity and to operate at high speed. In order to realize a large memory capacity, the memory cell area must be decreased, even if this requires that the current-driving ability of the memory cell transistor be decreased. Thus, it is necessary to develop a sense amplifier which operates at a small cell current.
A ROM is formed as shown in FIG. 1. 10 is a memory cell array comprising a plurality of word lines WL and bit lines BL, and a memory cell 10a provided at respective crossing portions of these word lines WL and bit lines BL. Memory cell 10a comprises, for example, a MOS transistor whose gate is connected to word line WL and whose drain is connected to bit line BL. Memory cell 10a may comprise a bipolar transistor. Word lines WL are selected by row decoder 11 and bit lines BL are selected by column decoder 12, and an address signal is input to these row and column decoders through address buffer 13. The read output of a bit line BL selected by the column decoder 12 is amplified by sense amplifier 14 and is outputted externally through output buffer 15.
That portion designated as sense amplifier 14, comprising a serial connection of load 21, transistor Q.sub.1 and memory cell 20, as shown in FIG. 2, is connected between power source V.sub.CC and ground GND. A potential at the crossing point of load 21 and transistor Q.sub.1 is detected by voltage output circuit 22. The source potential v.sub.a of transistor Q.sub.1 is inverted by inverter 23 and applied to a gate of transistor Q.sub.1. Memory cell 20 comprises a plurality of memory cells 20a, 20b . . . as shown in FIGS. 3A and 3B. FIG. 3A designates a serial type memory cell and FIG. 3B designates a parallel type memory cell. In a serial type memory, memory cells 20a, 20b . . ., which are formed of transistors, store either "1" or "0" depending on whether the transistor is of an enhancement type or of a depletion type. In a parallel type memory, "1" or "0" is stored depending on whether the threshold value is high or low.
In the configuration of FIG. 3A, the non-selection word line is made to level H and the selection word line is made to level L. When the word line WLb is selected, other word lines WLa, WLc, . . . are at H level and transistors 20a, 20c . . . are on regardless of whether the stored value is "1" or "0". Only transistor 20b, belonging to the selected word line, is turned on and off, depending on whether 1 or 0 is stored. If transistor 20b is of the depletion type it is on and if it is of the enhancement type it is off. Accordingly, depending on whether memory cell 20b is of the depletion type or the enhancement type, the data stored in memory cell 20b is determined to be 1 or 0, and thus a current flows or does not flow in bit line BLa. The potential V.sub.C at the connecting point between load 21 and transistor Q.sub.1 in FIG. 2 changes depending on whether or not the bit line current (i.sub.cel) flows and voltage output circuit 22 detects potential V.sub.C and produces read out data.
In the configuration of FIG. 3B, the selected word line is at H level and the non-selected word line is at L level. Accordingly, memory cells belonging to non-selected word lines are turned off regardless of whether "1" or "0" is stored, and only the memory cell belonging to the selected word line is turned on or off depending on whether "1" or "0" is stored. A current flows or does not flow in bit line BLa, depending on whether the memory cell is turned on or off, thereby changing the voltage V.sub.C. Voltage output circuit 22 then detects the voltage V.sub.C and produces the read-out data. Voltage output circuit 22 basically comprises only a line, but may be formed of a circuit for driving an output side circuit to be connected to the sense amplifier.
A column selection gate, which is turned on or off depending on the output of decoder 12, is provided between transistor Q.sub.1 and the bit line (cell group).
By making the slope of the input-output characteristic abrupt when inverter 23 in a transient state, the variation of the bit line voltage v.sub.a is suppressed, whether the bit line current I.sub.CEL is turned on or off. As shown in FIG. 5, when the cell is on, i.e., when the bit-line current flows, the voltage v.sub.a decreases, but the output v.sub.b of inverter 23 increases. When the cell is off, the voltage V.sub.a increases but the output V.sub.b of inverter 23 decreases quickly, thus decreasing the width of the variation of the voltage v.sub.a. This is effective for high speed operation. The voltage V.sub.C is equal to V.sub.CC -Rx.sub.icel under the condition that the resistance of load 21 is R and changes as shown in the drawing, depending on whether the cell is switched on or off.
Various kinds of inverters 23 are shown in FIGS. 4A to 4H. FIG. 4A shows an E-D type, FIG. 4B an E--E type, FIG. 4C and FIG. 4D CMOS types in which Qa is an n-channel enhancement type MOS transistor, Qb is an n-channel depletion type MOS transistor and Qd is a p-channel type MOS transistor. FIGS. 4E to 4H show only load portions. The gate of p-channel type transistor Qd is connected to ground in FIGS. 4C and 4G, connected to input IN in FIG. 4D and connected to the drain (output OUT) in FIG. 4H. The input-output characteristic of inverter 23 is shown in FIG. 6. When the input voltage v.sub.a is L (low), the output voltage v.sub.b is H (high), and when the input voltage v.sub.a is H (high), the output voltage v.sub.b is L (low). The input and the output characteristic changes proportionally between the above two states, as shown in FIG. 6. The variation width .DELTA.v.sub.a of the voltage v.sub.a in FIG. 6 is obtained from this proportionate area. Thus, the variation .DELTA.v.sub.b, which is expanded from the variation width .DELTA.v.sub.a, can be obtained. The boundary at which the transistor Q.sub.1 is turned on/off, is determined from v.sub.b -v.sub.a =V.sub.th1, assuming that V.sub.th1 is the threshold voltage of the transistor. P1 is a balance point at which the cell is turned off and P2 is the balance point when the cell is tuned on. The variation of voltage v.sub.a is small, as shown in FIG. 6.
For multi-value logic, the current is divided into several steps and for binary-value logic, the two states, i.e., the state in which current flows and the state in which current does not flow, are provided. Let us explain the example of two steps in which the current flows or does not flow.
As described above, the output of inverter 23 is fed back to the input of inverter 23 through transistor Q.sub.1. Moreover, the input-output characteristic of the inverter is abrupt. Therefore, the range of variation of v.sub.a can be made small, and v.sub.b can be changed quickly. That is, the variation of V.sub.a is made small so that the existence of a bit line capacitance shown in FIG. 7 does not greatly affect the operation of the cell 20, and the range of the variation in v.sub.b is made large, thus enabling the on/off control of transistor Q.sub.1 to be conducted at high speed and with certainty. When the memory cell is changed from a state in which current flows to a state in which current does not flow, the current stops flowing when v.sub.b -v.sub.a is equal to the V.sub.th of Q.sub.1 (at point P1). When a current flows in the memory cell, a charging operation of the bit line capacitance 24 is conducted and then completed. Thus, a current flowing through the bit line capacitance of the bit line is made 0. Thus, v.sub.b -v.sub.a changes until the current flowing into transistor Q.sub.1 becomes equal to the cell current (P.sub.2).
A column selection gate shown in FIG. 7 is connected between a cell 20 and a sense amplifier comprising transistor Q.sub.1, inverter 23 and load 21 and has a relatively large capacitance. As shown in FIG. 8, a parasitic capacitance C.sub.WB exists between bit line BL and word line WL. C.sub.BL is a parasitic capacitance existing between bit line BL and ground. The bit line potential is almost equal to v.sub.a. Thus, a change in v.sub.a means that the bit line potential changes and that the charges stored in bit line capacitances C.sub.BL and C.sub.WB change accordingly. When a current flows in the cell 20, the cell 20 has caused a discharge current of the bit line capacitance to flow, in addition to a sense current. The current flowing in the cell 20 and the sensed current differ in accordance with the amount of the discharge current. This is a factor contributing to access delay.
The fact that the change in v.sub.a is small means that the change in bit line potential is small and thus that the change in charge stored in the bit line is small, thereby decreasing the delay in access speed caused by the discharge current and providing an advantage of increased operation speed.
However, when the bit line potential exceeds that required for normal operation, the sense amplifier operates only after the excess charge is discharged by the cell transistor.
The reason for the above operation is that a variation in word line potential is reflected on a bit line by a parasitic capacitance C.sub.WB between a word line and a bit line and that an operation point of a sense amplifier varies in accordance with a power source potential variation caused by a noise.
Excess charge-up due to the power source voltage variation is explained by referring to FIGS. 9 and 10. The power source voltage is changed from an ordinary state (state A in FIG. 9) of a cell off-state at the power source voltage V.sub.CC to a state at power source voltage V.sub.CC +.DELTA.V. The input voltage v.sub.a of inverter 23 is detected under a new power source voltage V.sub.cc +.DELTA.V as if it would apparently decrease, thereby increasing v.sub.b (state B in FIG. 9, a.fwdarw.b in FIG. 10). As a result, current flows through transistor Q.sub.1 and the bit line capacitance is charged up. As a result, v.sub.a increases and v.sub.b decreases, thereby providing a new stable state under the voltage V.sub.CC +.DELTA.V (state C, b.fwdarw.c). When the source voltage is returned from this state to V.sub.CC, it is detected as if v.sub.a had increased and v.sub.b had decreased (state D, c.fwdarw.d). However, even if v.sub.b decreases by a large amount, transistor Q.sub.1 only turns off at a voltage of less than v.sub.b -v.sub.a =V.sub.th1 and the current supply is cut off. Therefore, v.sub.a maintains the present potential by means of a bit line capacitance (as shown by a dashed line in state E, d). When the state of the cell changes from OFF to ON as a result of an address selection by an addres signal ADDRESS, the excess charge is discharged through a cell transistor. The potential of v.sub.a decreases and the potential of v.sub.b increases (as shown by a dashed line in state F', d.fwdarw.a). After excess charge is discharged, until v.sub.b -v.sub.a &gt;V.sub.th1, an ordinary sense operation is carried out (state G, a.fwdarw.e). In the conventional current driving capability of a cell transistor, a time delay or a surplus time period shown in a state F' and d.fwdarw.a time delay is relatively unimportant, but when the current driving capability of the cell, i.e., the current driving capability by which the input-output characteristic is driven from d to e, becomes weak because of a fine pattern of the cell, the time delay in this surplus time period F' becomes large, greatly affecting access time.